// Combinational building block: multiplexor

module mux_2_1
(
    input  [3:0] d0,
    input  [3:0] d1,
    input        sel,
    output [3:0] y
);

    assign y = sel ? d1 : d0;

endmodule

module mux_4_1_imp_1
(
    input  [3:0] d0, d1, d2, d3,
    input  [1:0] sel,
    output [3:0] y
);

    assign y = sel [1]
        ? (sel [0] ? d3 : d2)
        : (sel [0] ? d1 : d0);

endmodule

module mux_4_1_imp_2
(
    input      [3:0] d0, d1, d2, d3,
    input      [1:0] sel,
    output reg [3:0] y
);

    <b><font color="red">
    // Using code for mux_4_1_imp_1 as a reference,
    // write code for 4:1 mux using "case" statement
    </font></b>









endmodule

module mux_4_1_imp_3
(
    input  [3:0] d0, d1, d2, d3,
    input  [1:0] sel,
    output [3:0] y
);

    <b><font color="red">
    // Construct 4:1 mux using three instances of mux_2_1 modules
    </font></b>

    

    
    
    

endmodule

module mux_4_1_bits_2
(
    input  [1:0] d0, d1, d2, d3,
    input  [1:0] sel,
    output [1:0] y
);

    assign y = sel [1]
        ? (sel [0] ? d3 : d2)
        : (sel [0] ? d1 : d0);

endmodule

module mux_4_1_imp_4
(
    input  [3:0] d0, d1, d2, d3,
    input  [1:0] sel,
    output [3:0] y
);

    <b><font color="red">
    // Construct 4:1 mux with 4-bit inputs and output
    // using two instances of mux_4_1 modules with 2-bit inputs and outputs
    </font></b>

    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //
    //

endmodule

module basys3_2
(
    input         clk,

    input         btnC,
    input         btnU,
    input         btnL,
    input         btnR,
    input         btnD,

    input  [15:0] sw,

    output [15:0] led,

    output [ 6:0] seg,
    output        dp,
    output [ 3:0] an
);

    mux_4_1_imp_1
    (
        <b><font color="red">
        // Write code that connects module's inputs and output:
        // d0      - to sw  [ 3: 0]
        // d1      - to sw  [ 7: 4]
        // d2      - to sw  [11: 8]
        // d3      - to sw  [15:12]
        // sel [1] - to btnC
        // sel [0] - to btnR
        // y       - to led [ 3: 0]
        </font></b>

        
        
        
        
        
        
    ); 
        
    assign seg = ~ 7'b0;
    assign dp  = 1'b1;
    assign an  = 4'b0;

endmodule

//--------------------------------------------------------------------

// Combinational building block: decoder

module decoder_3_8_imp_1
(
    input      [2:0] a,
    output reg [7:0] y
);

    always @*
    case (a)
    3'b000: y = 8'b00000001;
    3'b001: y = 8'b00000010;
    3'b010: y = 8'b00000100;
    3'b011: y = 8'b00001000;
    3'b100: y = 8'b00010000;
    3'b101: y = 8'b00100000;
    3'b110: y = 8'b01000000;
    3'b111: y = 8'b10000000;
    endcase

endmodule

module decoder_3_8_imp_2
(
    input      [2:0] a,
    output reg [7:0] y
);

    <b><font color="red">
    // Using decoder_3_8_imp_1 and decoder_3_8_imp_3 as references,
    // implement the decoder using "always" block and bit selection
    </font></b>

    //
    //
    //

endmodule

module decoder_3_8_imp_3
(
    input  [2:0] a,
    output [7:0] y
);

    assign y = 1 << a;

endmodule

module basys3_3
(
    input         clk,

    input         btnC,
    input         btnU,
    input         btnL,
    input         btnR,
    input         btnD,

    input  [15:0] sw,

    output [15:0] led,

    output [ 6:0] seg,
    output        dp,
    output [ 3:0] an
);

    decoder_3_8_imp_1 decoder_3_8_imp_1 (.a (sw [3:0]), .y (led [ 7:0]));
    decoder_3_8_imp_2 decoder_3_8_imp_3 (.a (sw [3:0]), .y (led [15:8]));

    assign seg = ~ 7'b0;
    assign dp  = 1'b1;
    assign an  = 4'b0;

endmodule

//--------------------------------------------------------------------

// Combinational building block: seven-segment driver

module single_digit_display
(
    input      [3:0] digit,
    input            single_digit,
    input            show_dot,

    output reg [6:0] seven_segments,
    output           dot,
    output     [3:0] anodes
);

    always @*
        case (digit)
        'h0: seven_segments = 'b1000000;  // a b c d e f g
        'h1: seven_segments = 'b1111001;
        'h2: seven_segments = 'b0100100;  //   --a--
        'h3: seven_segments = 'b0110000;  //  |     |
        'h4: seven_segments = 'b0011001;  //  f     b
        'h5: seven_segments = 'b0010010;  //  |     |
        'h6: seven_segments = 'b0000010;  //   --g--
        'h7: seven_segments = 'b1111000;  //  |     |
        'h8: seven_segments = 'b0000000;  //  e     c
        'h9: seven_segments = 'b0011000;  //  |     |
        'ha: seven_segments = 'b0001000;  //   --d-- 
        'hb: seven_segments = 'b0000011;


        'hc: <b><font color="red">/* Fill the missing code */</font></b>;


        'hd: seven_segments = 'b0100001;
        'he: seven_segments = 'b0000110;
        'hf: seven_segments = 'b0001110;
        endcase

    assign dot    = ~ show_dot;
    assign anodes = single_digit ? 4'b1110 : 4'b0000;

endmodule

//--------------------------------------------------------------------

module basys3_5
(
    input         clk,

    input         btnC,
    input         btnU,
    input         btnL,
    input         btnR,
    input         btnD,

    input  [15:0] sw,

    output [15:0] led,

    output [ 6:0] seg,
    output        dp,
    output [ 3:0] an
);

    single_digit_display single_digit_display
    (
        .digit           ( sw [3:0] ),
        .single_digit    ( sw [15]  ),
        .show_dot        ( sw [14]  ),

        .seven_segments  ( seg      ),
        .dot             ( dp       ),
        .anodes          ( an       )
    );

endmodule

//--------------------------------------------------------------------

// Sequential building block: counter

module clock_divider_100_MHz_to_1_49_Hz
(
    input  clock_100_MHz,
    input  resetn,
    output clock_1_49_Hz
);

    // 100 MHz / 2 ** 26 = 1.49 Hz

    reg [25:0] counter;

    always <b><font color="red">/* Fill the missing code */</font></b>


    begin
        if (! resetn)
            counter <= 0;
        else
            counter <= counter + 1;
    end

    <b><font color="red">// Write code connecting bit 25 of the counter to the output</font></b>



endmodule


module counter
(
    input             clock,
    input             resetn,
    output reg [15:0] count
);

    always @ (posedge clock or negedge resetn)
    begin
        if (! resetn)
            count <= 0;
        else
            count <= count + 1;
    end

endmodule


module basys3_6
(
    input         clk,

    input         btnC,
    input         btnU,
    input         btnL,
    input         btnR,
    input         btnD,

    input  [15:0] sw,

    output [15:0] led,

    output [ 6:0] seg,
    output        dp,
    output [ 3:0] an
);

    wire clock;
    wire resetn = ! btnU;

    clock_divider_100_MHz_to_1_49_Hz clock_divider
    (
        .clock_100_MHz (clk),
        .resetn        (resetn),
        .clock_1_49_Hz (clock)
    );

    counter counter
    (
        .clock  ( clock  ),
        .resetn ( resetn ),
        .count  ( led    )
    );

    assign seg = ~ 7'b0;
    assign dp  = 1'b0;
    assign an  = 4'b0;

endmodule