nexys4_ddr Wrapper for Digilent Nexys 4 DDR board with Xilinx Artix-7 FPGA

mfp_multi_switch_or_button_sync_and_debouncer mfp_switch_or_button_sync_and_debouncer Debouncer for the switches that control the clock mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz mfp_clock_divider BUFG Needed for the divided clock mfp_clock_divider_100_MHz_to_763_Hz Clock for 7-segment display mfp_multi_digit_display

mfp_system m14k_top The CPU core mfp_ejtag_reset mfp_ahb_lite_matrix_with_loader mfp_uart_receiver Receives data bytes from the PC via UART mfp_srec_parser Parses data received via UART as text in Motorola S-Record format and issues transactions to fill the system memory with this data mfp_srec_parser_to_ahb_lite_bridge Converts the transactions from S-Record parser into AHB-Lite protocol. Also converts virtual addresses into physical using fixed mapping mfp_ahb_lite_matrix mfp_ahb_lite_decoder mfp_ahb_ram_slave reset_ram mfp_dual_port_ram i0 mfp_dual_port_ram i1 mfp_dual_port_ram i2 mfp_dual_port_ram i3 mfp_ahb_ram_slave ram mfp_dual_port_ram i0 mfp_dual_port_ram i1 . . . . . . . . . . mfp_ahb_gpio_slave gpio mfp_ahb_lite_response_mux mfp_pmod_als_spi_receiver Receives data from the light sensor using a version of SPI protocol