MIPS Open and the current MIPS platforms: embedded Linux, automotive, datacenter and 5G

This text is a fragment of my conversation with Andreas Färber, a developer of openSUSE Linux. He was doing some MIPS, ARM and RISC/V ports. The conversation was initiated by Ivan Serdyuk, a developer from Ukraine.

The essence of MIPS Open

MIPS Open covers both MIPS R5 (which is a derivative of R2-R3) and R6. In the future it may cover possible R7, that is going to include R6, some improvement for AI data type support, and (most important) nanoMIPS architecture for high code density.

MIPS Open is not a single idea, but a combination of initiatives. Some background:

In the past, MIPS Technologies and Imagination Technologies were making money doing two things:

  1. Selling so-called core licenses for MIPS cores developed inside MIPS. Those cores were used by companies like Broadcom, Microchip, Infineon, Atheros (now a part of Qualcomm), MobilEye (now a part of Intel), Baikal Electronics in Russia etc. License for low-end cores like MIPS 4KEc, interAptiv UP, M5150, were ~$200K, license for high-end cores like MIPS 1074K, proAptiv, P5600 were over $1M. Deals with some companies were negotiated not as fixed license deals but based on royalty. A notable example of royalty-based deal is Microchip Technology, a microcontroller company with high volumes of MIPS M4K/microAptiv UP/M5100/M5150 — based 32-bit microcontrollers Microchip PIC32MX/MZ/MM.

  2. Selling so-called architecture licenses, a right to use MIPS architecture (the instruction set) to develop customer’s own core with their own microarchitecture (the organization of CPU pipeline and arithmetic units). Architecture licensees included Cavium with 64-bit networking MIPS cores of heir own design (now a part of Marvell), Broadcom (they had 64-bit MIPS cores of their design, and they also use some 32-bit
    cores licensed from MIPS Technologies), China’s Loongson project (64-bit laptops with MIPS and Linux), etc. Architecture license was more expensive than core licenses because cores created under architecture licenses effectively competed against cores created under core licenses. Architecture license was usually several million dollars sometimes more than $10M

Right now, with MIPS Open, the situation changes. Architecture license essentially becomes free. Anybody can use MIPS instruction set, just like RISC/V instruction set. But there are two difference:

  1. Wave/MIPS gives to MIPS architecture users a set of architecture tests to verify they whatever they designed is truly MIPS. This avoids architecture fragmentation.

  2. MIPS Open protects the designers of MIPS-compatible cores with patent protection against lawsuits from other processor designers.

In addition to making the architecture free, we open source of some cores written in hardware description language Verilog, to the public. As you probably know, most of embedded processors are created using RTL2GDSII flow, where Verilog code is synthesized into netlist, place and routed to create GDSII file with a mask blueprint that is sent to a fab like TSMC.

Alternatively this Verilog code can be synthesized into FPGA configuration. So effectively you can create a processor inside FPGA. For small processors like MIPS interAptiv UP you can use cheap FPGA boards like Altera DE10-Lite for $85, for large processors you may need FPGA boards that cost $30,000 or more. Intel uses for prototyping of their x86-64 processors FPGA-based ZeBu emulator that can emulate billions of gates but cost probably more than million dollar.

So the first core with Verilog core you can play under MIPS Open is MIPS microAptiv UP which was used in the past by Microchip inside their PIC32 microcontrollers. This is essentially an extension of the academic program MIPSfpga. You can read about it in https://github.com/MIPSfpga/mipsfpga-plus/wiki.

The status of publicly announced MIPS platforms.

  1. Right now MIPS has four priority publicly announced commercial projects:

    1. 32-bit chip (mid-range dual-issue in-order pipeline core MIPS I7200 with multithreading support) for 5G model with MediaTek.

    2. 64-bit automotive chips designed together with MobilEye and DENSO. MobilEye is a part of Intel. MobilEye’s chips are inside ADAS (Advanced Driver Assistance Systems) in BMW, Volvo and other major car manufacturer solutions. DENSO is a company that designs electronics for Toyota. There chips are based on in-order multithreaded core MIPS I6400 and its cluster I6500 Daimyo.

    3. MIPS AI processor, also based on MIPS I6500 for Wave’s AI needs.

    4. Datacenter storage chip with Fungible, also based on MIPS I6500.

  2. There are some cool IoT projects based on old MIPS 24K core, most notably Omega Onion2 and LinkIt Smart, both use MediaTek MT7688 chip and OpenWRT. This is an interesting platform for embedded Linux IoT and can be used for educational purposes as a low-power substitute for Raspberry Pi.

  3. There are MIPS-based Microchip PIC32 chips, but only some of them can run very stripped-down Linux, specifically PIC32MZ that have MIPS M5150 with TLB MMU. They can also be used for microcontroller education and labs with RTOS.

  4. There is a virtualization-capable high-end platform based on Baikal BE-T1000 processor. This chip is designed in Russia based on two-core cluster of MIPS P5600 Apache cores (R5 cores). See SoC From Russia With MIPS. This chip runs Debian and BaseALT Linux. A board with this chip can be bought on Russian website ChipDip for $600. This is a good chip used in a dozen of devices including thin client.

  5. There is an effort to port Linux on MIPS Open / MIPSfpga / MIPS microAptiv UP (R5 core) running on Altera / Intel FPGA board

Yuri Panchul, May 12, 2019