Tag Archives: midterm

Intro RTL design for FPGA using Verilog. Midterm exam 1, variant 5

1.5 Which waveform is the result of the simulation below? module design (input a, input b, output o); assign o = a ^ b; endmodule module tb; logic a, b, o; design design_inst (a, b, o); initial begin $dumpvars; $monitor ("%t a %b b %b o %b", $time, a, b, o); #10; a = 0; […] Дальше …

Intro RTL design for FPGA using Verilog. Midterm exam 1, variant 4

1.4 Which waveform is the result of the simulation below? module design (input a, input b, output o); assign o = a | b; endmodule module tb; logic a, b, o; design design_inst (a, b, o); initial begin $dumpvars; $monitor ("%t a %b b %b o %b", $time, a, b, o); #10; a = 0; […] Дальше …

Intro RTL design for FPGA using Verilog. Midterm exam 1, variant 3

1.3 Which waveform is the result of the simulation below? module design (input a, input b, output o); assign o = a & b; endmodule module tb; logic a, b, o; design design_inst (a, b, o); initial begin $dumpvars; $monitor ("%t a %b b %b o %b", $time, a, b, o); #10; a = 0; […] Дальше …

Intro RTL design for FPGA using Verilog. Midterm exam 1, variant 2

1.2 Which waveform is the result of the simulation below? module design (input a, input b, output o); assign o = ~ a | ~ b; endmodule module tb; logic a, b, o; design design_inst (a, b, o); initial begin $dumpvars; $monitor ("%t a %b b %b o %b", $time, a, b, o); #10; a […] Дальше …

Intro RTL design for FPGA using Verilog. Midterm exam 1, variant 1

1.1 Which waveform is the result of the simulation below? module design (input a, input b, output o); assign o = ~ a & ~ b; endmodule module tb; logic a, b, o; design design_inst (a, b, o); initial begin $dumpvars; $monitor ("%t a %b b %b o %b", $time, a, b, o); #10; a […] Дальше …